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Integrated Circuit Systems, Inc.
ICS950703
Programmable Timing Control HubTM for P4TM
Recommended Application: Intel Tehema and Tehema-E Chipsets Output Features: * 4 Differential CPU Clock Pairs @ 3.3V * 2 - 3V MREF clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) * 4 - 66MHz 3V66 output * 10 - 3V 33MHz PCI clocks * 2 - 48MHz clocks (180 degrees out of phase) * 2 - 14.318 reference output (180 degrees out of phase) Key Specifications: * 3V66 Output jitter <300ps * CPU Output Jitter <200ps * MREF Output jitter <250ps Features/Benefits: * QuadRomTM frequency selection. * Programmable asynchronous 3V66/PCI frequency. * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz reference input.
Frequency Table
Bit4 Sel133/100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 90.00 100.00 100.90 103.00 105.00 108.00 110.00 112.00 115.00 118.00 120.00 122.00 125.00 127.00 130.00 133.60 120.00 133.33 133.90 136.00 138.00 140.00 142.00 144.00 145.00 148.00 150.00 152.00 154.00 156.00 158.00 160.00 MREF MHz 45.00 50.00 50.45 51.50 52.50 54.00 55.00 56.00 57.50 59.00 60.00 61.00 62.50 63.50 65.00 66.80 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 PCI MHz 30.00 33.33 33.63 34.33 35.00 36.00 36.67 37.33 38.33 39.33 40.00 40.67 41.67 42.33 43.33 44.53 30.00 33.33 33.48 34.00 34.50 35.00 35.50 36.00 36.25 37.00 37.50 38.00 38.50 39.00 39.50 40.00 3V66 MHz 60.00 66.67 67.27 68.67 70.00 72.00 73.33 74.67 76.67 78.67 80.00 81.33 83.33 84.67 86.67 89.07 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00
Pin Configuration
GND 1 MULTSEL0/REF0 2 MULTSEL1/REF1 3 VDDREF 4 X1 5 X2 6 GNDREF 7 PCICLK0 8 PCICLK1 9 VDDPCI 10 PCICLK2 11 GNDPCI 13 PCICLK4 14 PCICLK5 15 VDDPCI 16 PCICLK6 17 **FS2/PCICLK7 18 GNDPCI 19 **FS3/PCICLK8 20 **SEL100_133#/PCICLK9 21 VDDPCI 22 SDATA 23 GND48 24 *FS0/48MHz_0 25 **FS1/48MHz_1 26 AVDD48 27 PD# 28 56-SSOP 56 VDDMREF 55 3VMREF 54 3VMREF_B 53 GNDMREF 52 SCLK 51 CPUCLKT3 50 CPUCLKC3 49 VDDCPU 48 CPUCLKT2 47 CPUCLKC2 46 GNDCPU
ICS950703
PCICLK3 12
45 CPUCLKT1 44 CPUCLKC1 43 VDDCPU 42 CPUCLKT0 41 CPUCLKC0 40 GNDCPU 39 IREF 38 AVDD 37 GND 36 VDD3V66 35 3V66_3 34 3V66_2 33 GND3V66 32 GND3V66 31 3V66_1 30 3V66_0 29 VDD3V66
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
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ICS950703
General Description
The ICS950703 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with Rambus RDRAM memory. It provides all necessary clock signals for such a system. The ICS950703 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/ N control can configure output frequency with resolution up to 0.1MHz increment. This part also provides 128 frequency selections via ICS QuadROMTM technology as an alternate to M/N programming.
Block Diagram
PLL2 Frequency Dividers 48MHZ (1:0)
X1 X2
XTAL
REF (1:0)
4 4
CPUCLKT (3:0) CPUCLKC (3:0) PCICLK (9 :0) MREF MREF_B 3V66 (3:0)
MULTSEL (1:0) FS (3:0) SEL100_133# SDATA SCLK PD# Control Logic Programmable Spread PLL1 Programmable Frequency Dividers
STOP Logic
I REF
Power Groups
Pin Number AVDD 4 27 38 VDD 10, 16, 22 29, 36 43, 49 56 GND 7 24 37 GND 13, 19 32, 33 40, 46 53 Description REF output, Crystal 48MHz fixed, Fixed PLL CPU PLL, CPU Master Clock, -PCI outputs 3V66 outputs CPU Outputs, IREF, MULTSEL MREF outputs
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Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND MULTSEL0/REF0 MULTSEL1/REF1 VDDREF X1 X2 GNDREF PCICLK0 PCICLK1 VDDPCI PCICLK2 PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 **FS2/PCICLK7 GNDPCI **FS3/PCICLK8 **SEL100_133#/PCICLK9 VDDPCI SDATA GND48 *FS0/48MHz_0 **FS1/48MHz_1 AVDD48 PD# PIN NAME PIN TYPE DESCRIPTION
PWR Ground pin. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference I/O clock. 3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference I/O clock. PWR Ref, XTAL power supply, nominal 3.3V I/O I/O Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output.
PWR Ground pin for the REF outputs. OUT PCI clock output. I/O Watchdog enable latch input/ 3.3V PCI clock output. PWR Power supply for PCI clocks, nominal 3.3V OUT PCI clock output. OUT PCI clock output. PWR Ground pin for the PCI outputs OUT PCI clock output. OUT PCI clock output. PWR Power supply for PCI clocks, nominal 3.3V OUT PCI clock output. I/O I/O Frequency select latch input pin / 3.3V PCI clock output. PWR Ground pin for the PCI outputs Frequency select latch input pin / 3.3V PCI clock output. Latched select input for 100 or 133.3MHz selection. 0=133MHz, 1 = 100MHz / 3.3V PCI I/O clock output. PWR Power supply for PCI clocks, nominal 3.3V I/O I/O I/O Data pin for SMBus circuitry, 5V tolerant. Frequency select latch input pin / Fixed 48MHz clock output. 3.3V Frequency select latch input pin / Fixed 48MHz clock output. 3.3V PWR Ground pin for the 48MHz outputs
PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V IN Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
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Pin Description (Continued)
PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VDD3V66 3V66_0 3V66_1 GND3V66 GND3V66 3V66_2 3V66_3 VDD3V66 GND AVDD IREF GNDCPU CPUCLKC0 CPUCLKT0 VDDCPU CPUCLKC1 CPUCLKT1 GNDCPU CPUCLKC2 CPUCLKT2 VDDCPU CPUCLKC3 CPUCLKT3 SCLK GNDMREF 3VMREF_B 3VMREF VDDMREF PIN NAME PIN TYPE PWR Power pin for the 3V66 clocks. OUT 3.3V 66.66MHz clock output OUT 3.3V 66.66MHz clock output PWR Ground pin for the AGP outputs PWR Ground pin for the AGP outputs OUT 3.3V 66.66MHz clock output OUT 3.3V 66.66MHz clock output PWR Power pin for the 3V66 clocks. PWR Ground pin. PWR 3.3V Analog Power pin for Core PLL This pin establishes the reference current for the differential current-mode output pairs. This OUT pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the CPU outputs Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Ground pin for the CPU outputs Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. PWR Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External OUT resistors are required for voltage bias. IN Clock pin of SMBus circuitry, 5V tolerant. PWR Ground pin for the 3VMREF outputs. OUT 3V reference output to memory clock driver (180 degree out of phase with 3VMREF) OUT 3V reference output to memory clock driver PWR Power supply for 3VMREF clocks, nominal 3.3V DESCRIPTION
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 2X drive
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ICS950703
Maximum Allowed Current Pin Description
Condition Powerdown Mode (PWRDWN# = 0) Full Active Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 BYTE 1 BIT 3 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 4*Iref Ioh = 4*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 5*Iref Ioh = 5*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.56V @ 60 0.47V @ 50 0.85V /2 60 0.71V @ 50 0.71V @ 60 0.59V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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ICS950703
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Table1: QuadRom Frequency Selection Table Bit6 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit5 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit4 Sel133/100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 90.00 100.00 100.90 103.00 105.00 108.00 110.00 112.00 115.00 118.00 120.00 122.00 125.00 127.00 130.00 133.60 120.00 133.33 133.90 136.00 138.00 140.00 142.00 144.00 145.00 148.00 150.00 152.00 154.00 156.00 158.00 160.00 MREF MHz 45.00 50.00 50.45 51.50 52.50 54.00 55.00 56.00 57.50 59.00 60.00 61.00 62.50 63.50 65.00 66.80 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00 PCI MHz 30.00 33.33 33.63 34.33 35.00 36.00 36.67 37.33 38.33 39.33 40.00 40.67 41.67 42.33 43.33 44.53 30.00 33.33 33.48 34.00 34.50 35.00 35.50 36.00 36.25 37.00 37.50 38.00 38.50 39.00 39.50 40.00 3V66 MHz 60.00 66.67 67.27 68.67 70.00 72.00 73.33 74.67 76.67 78.67 80.00 81.33 83.33 84.67 86.67 89.07 60.00 66.67 66.95 68.00 69.00 70.00 71.00 72.00 72.50 74.00 75.00 76.00 77.00 78.00 79.00 80.00
Notes:
Table1 continues on the next three pages.
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ICS950703
QuadRomTM Frequency Selection Table
Description Bit6 Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ 456.00 460.00 464.00 468.00 472.00 476.00 480.00 484.00 488.00 492.00 500.00 508.00 516.00 524.00 532.00 540.00 456.00 459.00 462.00 465.00 468.00 471.00 474.00 477.00 480.00 483.00 486.00 489.00 492.00 495.00 498.00 501.00 CPUCLK MHz 114.00 115.00 116.00 117.00 118.00 119.00 120.00 121.00 122.00 123.00 125.00 127.00 129.00 131.00 133.00 135.00 152.00 153.00 154.00 155.00 156.00 157.00 158.00 159.00 160.00 161.00 162.00 163.00 164.00 165.00 166.00 167.00 3V66 MHz 76.00 76.67 77.33 78.00 78.67 79.33 80.00 80.67 81.33 82.00 83.33 84.67 86.00 87.33 88.67 90.00 76.00 76.50 77.00 77.50 78.00 78.50 79.00 79.50 80.00 80.50 81.00 81.50 82.00 82.50 83.00 83.50 PCICLK MHz 38.00 38.33 38.67 39.00 39.33 39.67 40.00 40.33 40.67 41.00 41.67 42.33 43.00 43.67 44.33 45.00 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.00 40.25 40.50 40.75 41.00 41.25 41.50 41.75
Sel133/100 FS3 FS2 FS1 FS0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Notes:
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Continuation of Table1 from previous page.
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ICS950703
QuadRomTM Frequency Selection Table
Description Bit6 Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ 400.02 408.00 420.00 432.00 444.00 456.00 468.00 480.00 492.00 504.00 516.00 528.00 540.00 552.00 564.00 576.00 588.00 600.00 612.00 624.00 636.00 648.00 660.00 672.00 666.68 668.00 672.00 676.00 680.00 684.00 688.00 692.00 CPUCLK MHz 66.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 94.00 96.00 98.00 100.00 102.00 104.00 106.00 108.00 110.00 112.00 166.67 167.00 168.00 169.00 170.00 171.00 172.00 173.00 3V66 MHz 66.67 68.00 70.00 72.00 74.00 76.00 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 94.00 96.00 98.00 100.00 102.00 104.00 106.00 108.00 110.00 112.00 66.67 66.80 67.20 67.60 68.00 68.40 68.80 69.20 PCICLK MHz 33.34 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 33.33 33.40 33.60 33.80 34.00 34.20 34.40 34.60
Sel133/100 FS3 FS2 FS1 FS0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Notes:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Continuation of Table1 from previous page.
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ICS950703
QuadRomTM Frequency Selection Table
Description Bit6 Bit5 Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO MHZ 696.00 700.00 704.00 708.00 712.00 716.00 720.00 724.00 320.00 330.00 340.00 350.00 360.00 370.00 380.00 390.00 400.00 402.00 404.00 406.00 408.00 412.00 416.00 420.00 424.00 428.00 432.00 436.00 440.00 444.00 448.00 452.00 CPUCLK MHz 174.00 175.00 176.00 177.00 178.00 179.00 180.00 181.00 160.00 165.00 170.00 175.00 180.00 185.00 190.00 195.00 200.00 201.00 202.00 203.00 204.00 206.00 208.00 210.00 212.00 214.00 216.00 218.00 220.00 222.00 224.00 226.00 3V66 MHz 69.60 70.00 70.40 70.80 71.20 71.60 72.00 72.40 53.33 55.00 56.67 58.33 60.00 61.67 63.33 65.00 66.67 67.00 67.33 67.67 68.00 68.67 69.33 70.00 70.67 71.33 72.00 72.67 73.33 74.00 74.67 75.33 PCICLK MHz 34.80 35.00 35.20 35.40 35.60 35.80 36.00 36.20 26.67 27.50 28.33 29.17 30.00 30.83 31.67 32.50 33.33 33.50 33.67 33.83 34.00 34.33 34.67 35.00 35.33 35.67 36.00 36.33 36.67 37.00 37.33 37.67
Sel133/100 FS3 FS2 FS1 FS0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
Notes:
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Continuation of Table1 from previous page.
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I2C Table: Frequency Select Register Byte 0 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FS Source FS6 FS5 FS4 FS3 FS2 FS1 FS0
Control Function Frequency H/W IIC Select Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Selcet Bit 0
Type RW RW RW RW RW RW RW RW
0 Latch Inputs
1 IIC
PWD 0 0 0 0 0 0 0 1
See Table 1: Quad TM Rom Frequency Selection Table
I2C Table: Spreading, Device Behavior and Output Control Register Byte 1 Pin # Name Control Function Type Bit 7 RW SS1 Spread Select 1 Bit 6 SS0 Spread Select 0 RW Spread Enable Bit 5 SSEN RW Control Bit 4 Reserved Reserved RW 51/50 Bit 3 RW CPUT/C3 Output Control 48/47 Bit 2 CPUT/C2 Output Control RW 45/44 Bit 1 CPUT/C1 Output Control RW 42/41 Bit 0 CPUT/C0 Output Control RW
0 1 See Table 2: Spread Spectrum Table Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable
PWD 0 0 0 0 1 1 1 1
Table2: Spread Spectrum Select
SS1 (Byte 1 bit 7) 0 0 1 1 SS0 (Byte 1 bit 6) 0 1 0 1 Spread % 0.35% 0.50% 0.70% 1.00% Downspread % 0.32% 0.45% 0.75% 1.00% Note Default Spread 2 Spread 3 Spread 4
I2C Table: Output Control Register Byte 2 Pin # Name 18 Bit 7 PCICLK7 17 Bit 6 PCICLK6 15 Bit 5 PCICLK5 14 Bit 4 PCICLK4 12 Bit 3 PCICLK3 11 Bit 2 PCICLK2 9 Bit 1 PCICLK1 8 Bit 0 PCICLK0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
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I2C Table: Output Control Register Byte 3 Pin # Name 26 Bit 7 48MHz_1 25 Bit 6 48MHz_0 Bit 5 Reserved Bit 4 Reserved 55 Bit 3 3VMREF 54 Bit 2 3VMREF_B 21 Bit 1 PCICLK_9 20 Bit 0 PCICLK_8 I2C Table: Output Control Register Byte 4 Pin # Name 3 Bit 7 REF1 2 Bit 6 REF0 Bit 5 Reserved 35 Bit 4 3V66_3 Bit 3 Reserved 34 Bit 2 3V66_2 31 Bit 1 3V66_1 30 Bit 0 3V66_0 I2C Table: Output Control Register Byte 5 Pin # Name Bit 7 Reserved Bit 6 PLL2EN Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AEN AFS4 AFS3 AFS2 AFS1 AFS0
Control Function Output Control Output Control Reserved Reserved Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable
PWD 1 1 0 1 1 1 1 1
Control Function Output Control Output Control Reserved Output Control Reserved Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
Control Function Reserved FIX_2 PLL Control 3V66/PCI Freq Source Select Async Rom SEL_2 Async Rom SEL_1 Async Rom SEL_0 Async Divider SEL_1 Async Divider SEL_0
Type RW RW RW RW RW RW RW RW
0 OFF CPU_PLL Sync
1 ON FIX_PLL Async
PWD 0 1 0 0 0 0 0 1
See Table 3: Async 3V66/PCI Frequency Selection Table
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Table 3: Async 3V66/PCI Frequency Selection Table Byte 5 Bit4 Byte 5 Bit3 Byte 5 Bit2 Byte 5 Bit1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Byte 5 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3V66 66.00 74.25 84.86 99.00 64.00 72.00 82.29 96.00 59.26 66.67 76.19 88.89 67.22 75.63 86.43 100.83 70.00 78.75 90.00 105.00
PCI 33.00 37.13 42.43 49.50 32.00 36.00 41.15 48.00 29.63 33.34 38.10 44.45 33.61 37.82 43.22 50.42 35.00 39.38 45.00 52.50
I2C Table: Read Back Register Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -
Name WDHRB
MULTSEL0 MULTSEL1 SEL100/ 133#RB FS3RB FS2RB FS1RB FS0RB
Control Function WD Hard Alarm Status Read back MULTSEL0 Read back MULTISEL1 Read back SEL100/133 # Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back
Type R R R R R R R R
0 -
1 -
PWD X X X X X X X X
I2C Table: Vendor & Revision ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0
Control Function REVISION ID
VENDOR ID
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 1 0 0 0 1
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I2C Table: Byte Count Register Byte 8 Pin # Name Bit 7 BC7 Bit 6 BC6 Bit 5 BC5 Bit 4 BC4 Bit 3 BC3 Bit 2 BC2 Bit 1 BC1 Bit 0 BC0 I2C Table: Watchdog Timer Register Byte 9 Pin # Name Bit 7 WD7 Bit 6 WD6 Bit 5 WD5 Bit 4 WD4 Bit 3 WD3 Bit 2 WD2 Bit 1 WD1 Bit 0 WD0
Control Function Writing to this register will configure how many bytes will be read back, default is 0FH = 15 bytes.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 1 1 1 1
Control Function These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 10*290ms = 2.9 seconds.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 1 0 1 0
I2C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Control Function M/N Programming Bit 7 M/NEN Enable Bit 6 WD Enable WD Enable WD Safe Frequency Bit 5 WD SF Mode Mode Bit 4 WDSF4 Writing to these bit Bit 3 WDSF3 will configure the Bit 2 WDSF2 safe frequency as Bit 1 WDSF1 Byte 0 Bit (4:0) Bit 0 WDSF0 I2C Table: VCO Frequency Control Register Byte 11 Pin # Name Control Function Bit 7 NDiv8 N Divider Bit 8 The decimal Bit 6 MDiv6 representation of M Bit 5 MDiv5 Div (6:0) + 2 is equal Bit 4 MDiv4 to reference divider Bit 3 MDiv3 Bit 2 value. Default at MDiv2 Bit 1 MDiv1 power up = latch-in Bit 0 MDiv0 or Byte 0 Rom table.
Type RW RW RW RW RW RW RW RW
0 Disable Disable Latched Inputs -
1 Enable Enable B10 Bit(4:0) -
PWD 0 0 0 0 0 0 0 0
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
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I2C Table: VCO Frequency Control Register Byte 12 Pin # Name Control Function Bit 7 NDiv7 The decimal Bit 6 NDiv6 representation of N Bit 5 NDiv5 Div (8:0) +8 is equal Bit 4 NDiv4 to VCO divider Bit 3 NDiv3 value. Default at Bit 2 NDiv2 power up = latch-in Bit 1 NDiv1 or Byte 0 Rom table. Bit 0 NDiv0 I2C Table: Spread Spectrum Control Register Byte 13 Pin # Name Control Function These Spread Bit 7 SSP7 Spectrum bits will Bit 6 SSP6 program the spread Bit 5 SSP5 pecentage. It is Bit 4 SSP4 recommended to Bit 3 SSP3 Bit 2 SSP2 use ICS Spread % Bit 1 SSP1 table for spread Bit 0 SSP0 programming. I2C Table: Spread Spectrum Control Register Byte 14 Pin # Name Control Function Bit 7 Reserved Reserved Bit 6 Reserved Reserved Bit 5 SSP13 It is recommended to Bit 4 SSP12 use ICS Spread % Bit 3 SSP11 table for spread Bit 2 SSP10 Bit 1 SSP9 programming. Bit 0 SSP8 I2C Table: Output Divider Control Register Byte 15 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 CPUDiv3 Bit 2 CPUDiv2 Bit 1 CPUDiv1 Bit 0 CPUDiv0
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
Type R R R RW RW RW RW RW
0 -
1 -
PWD 0 0 X X X X X X
Control Function Reserved Reserved Reserved Reserved CPU divider ratio can be configured via these 4 bits individually.
Type RW RW RW RW RW RW RW RW
0 -
1 -
See Table 4: Divider Ratio Combination Table
PWD X X X X X X X X
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Table 4: Divider Ratio Combination Table (CPU & MREF)
Divider (3:2) Bit Divider (1:0) 00 01 10 11 LSB 00 1 0000 0001 0010 0011 Address 2 3 5 7 Div 0100 0101 0110 0111 Address 01 2 4 6 10 14 Div 1000 1001 1010 1011 Address 10 4 8 12 20 28 Div 1100 1101 1110 1111 Address 11 MSB 8 16 24 40 56 Div
I2C Table: Output Divider Control Register Byte 16 Pin # Name Control Function PCI divider ratio can Bit 7 PCIDiv3 be configured via Bit 6 PCIBit 2 these 4 bits Bit 5 PCIDiv4 Bit 4 PCIBit 3 individually. 3V66 divider ratio Bit 3 3V66Div3 can be configured Bit 2 3V66Div2 via these 4 bits Bit 1 3V66Div1 Bit 0 individually. 3V66Div0 I2C Table: Output Divider Control Register Byte 17 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCIINV 3V66 3V66INV Reserved CPUINV Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0
1
See Table 4: Divider Ratio Combination Table See Table 4: Divider Ratio Combination Table
PWD X X X X X X X X
Control Function PCI 3V66 Phase Invert 3V66 Phase Invert Reserved CPU Phase Invert Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 Default Default Default -
1 Inverse Inverse Inverse -
PWD X X X X X X X X
I2C Table: Group Skew Control Register Byte 18 Pin # Name Bit 7 CPUSkw1 Bit 6 CPUSkw0 Bit 5 Reserved Bit 4 Reserved Bit 3 CPUSkw1 Bit 2 CPUSkw0 Bit 1 Reserved Bit 0 Reserved
Control Function CPUC/T(2:1) to CPU C/T(3,0) Skew Cntrol Reserved Reserved CPUC/T(3,0) to CPU C/T(2:1) Skew Cntrol Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 1 See Table 5: 2-bit Skew Control Table See Table 5: 2-bit Skew Control Table -
PWD 1 1 1 1 1 1 1 1
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Table 5: 2 Bits Skew Programming Table
4 Step 0 1 MSB 0 0ps 500ps 1 250ps 750ps LSB -
I2C Table: Group Skew Control Register Byte 19 Pin # Name Bit 7 MREFSkw3 Bit 6 MREFSkw2 Bit 5 MREFSkw1 Bit 4 MREFSkw0 Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved I2C Table: Group Skew Control Register Byte 20 Pin # Name Bit 7 PCISkw3 Bit 6 PCISkw2 Bit 5 PCISkw1 Bit 4 PCISkw0 Bit 3 PCISkw3 Bit 2 PCISkw2 Bit 1 PCISkw1 Bit 0 PCISkw0
Control Function CPUC/T to MREF/MREF_B Skew Cntrol Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0
1
See Table 6: 7-Steps Skew Control Table -
PWD 0 1 0 0 0 1 0 0
Control Function CPU to PCI(9:6) Skew Control
CPU to PCI(5:0) Skew Control
Type RW RW RW RW RW RW RW RW
0
1
See Table 6: 7-Steps Skew Control Table
See Table 6: 7-Steps Skew Control Table
PWD 0 1 1 0 0 1 1 0
Table 6: 7-Steps Skew Programming Table
7 Step 11 10 01 00 MSB 11 900 ps N/A N/A N/A 10 750 ps N/A N/A N/A 01 600 ps N/A N/A N/A 00 450 ps 300 ps 150 ps 0.0 ps LSB
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I2C Table: Group Skew Control Register Byte 21 Pin # Name Bit 7 3V66Skw1 Bit 6 3V66Skw0 Bit 5 Reserved Bit 4 Reserved Bit 3 3V66Skw1 Bit 2 3V66Skw0 Bit 1 Reserved Bit 0 Reserved I2C Table: Slew Rate Control Register Byte 22 Pin # Name Bit 7 48MHzSlw1 Bit 6 48MHzSlw0 Bit 5 48MHzSlw1 Bit 4 48MHzSlw0 Bit 3 3V66Slw1 Bit 2 3V66Slw0 Bit 1 3V66Slw1 Bit 0 3V66Slw0 I2C Table: Slew Rate Control Register Byte 23 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 PCISlw1 Bit 4 PCISlw0 Bit 3 PCISlw1 Bit 2 PCISlw0 Bit 1 PCISlw1 Bit 0 PCISlw0 I2C Table: Slew Rate Control Register Byte 24 Pin # Name Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 REFSlw1 Bit 2 REFSlw0 Bit 1 REFSlw1 Bit 0 REFSlw0
Control Function CPU to 3V66(3:2) Skew Control Reserved Reserved CPU to 3V66(1:0) Skew Control Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 1 See Table 5: 2-bit Skew Control Table See Table 5: 2-bit Skew Control Table -
PWD 0 0 0 0 0 0 0 0
Control Function 48MHz_0 Slew Rate Control 48MHz_1 Slew Rate Control 3V66 (0) Slew Rate Control 3V66 (3:1) Slew Rate Control
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 1 0 1 0 1 0 1 0
Control Function Reserved Reserved PCI (9:7), (5:2) Slew Rate Control PCI (6) Slew Rate Control PCI (1:0) Slew Rate Control
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 1 0 1 0 1 0 1 0
Control Function Reserved Reserved Reserved Reserved REF1 Slew Rate Control REF0 Slew Rate Control
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 1 0 1 0
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Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage SYMBOL VIH VIL IIH Input High Current IIH IIL1 Input Low Current IIL2 Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance
1
CONDITIONS
MIN 2 V SS - 0.3 -200
TYP
MAX UNITS V DD + 0.3 V 0.8 V 200 5 A mA A mA
VIN = VDD; Inputs with no pull-down resistors VIN = VDD; Inputs with pull-down resistors VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=5 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
-200 -5 229 220 230 233 35 14.318
200
IDD3.3OP IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB tPZH,t PZL tPHZ,t PLZ
360 360 45
27
36 1
5 6 45 3 10 10
mA mA mA MHz nH pF pF pF ms ns ns
Clk Stabilization1,2 Delay 1
1 2
1 1
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
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Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70C; VDD=3.3V Rs=33 , Rp(pulldown) = 50 (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Statistical measurement on single ended Voltage High VHigh signal using oscilloscope math function. VLow Voltage Low Measurement on single ended signal Vovs Max Voltage using absolute value. Vuds Min Voltage tr VOL = 0.175V, VOH = 0.525V Rise Time VOH = 0.525V VOL = 0.175V tf Fall Time Duty Cycle Skew Jitter, Cycle to cycle
1 2
MIN 660 -150 -450 175 175 45
TYP 788 16 818 11 306 330 50.2 120 49
MAX 850 150 1150 700 700 55 150 150
UNITS mV mV ps ps % ps ps
dt3 tsk3
1 tjcyc-cyc
Measurement from differential wavefrom VT = 50% VT = 50%
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - MREF/MREF_B
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance V O = VDD*(0.5) RDSP11 1 Output High Voltage IOH = -1 mA V OH Output Low Voltage Output High Current Output Low Voltage Rise Time Fall Time Duty Cycle Jitter
1
MIN 12 2.4
TYP
MAX 65 0.4
UNITS MHz V V mA mA ns ns % ps
V OL
1
I OL = 1 mA V V
OH@MIN
IOH1 IOL1 t r11 t f11 dt11 t jcyc-cyc
1
= 1.0 V, Voh@MAX=3.135
-33 30 0.5 0.5 45 1.8 1.7 54 138
-33 38 2 2 55 250
OH@MIN = 1.95 V, Voh@MAX=0.4
V OL = 0.4 V, VOH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance V O = VDD*(0.5) RDSP11 1 IOH = -1 mA Output High Voltage V OH Output Low Voltage Output High Current Output Low Voltage Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 66.66
MAX 65 0.4
UNITS MHz V V mA mA ns ns % ps ps
V OL IOL t r1
1
I OL = 1 mA V V
OH@MIN
IOH1
1 1
= 1.0 V, Voh@MAX=3.135 = 1.95 V, Voh@MAX=0.4
-33 30 0.5 0.5 45 1.8 1.51 50 52 160
-33 38 2 2 55 250 250
OH@MIN
V OL = 0.4 V, VOH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V V T = 1.5 V
1
t f11 dt11 tsk1
1
t jcyc-cyc
VT = 1.5 V 3V66
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP1 1 VOH 1 VOL 1 IOH 1 IOL 1 tr1 1 tf1 1 dt1
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V VOL @MIN = 1.95 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP 14.32
MAX 60 0.4 -23 27 4 4 55 350
UNITS MHz V V
1.15 1.4 52.5 184
ns ns % ps
tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
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ICS950703
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 V O = VDD*(0.5) Output Impedance RDSP11 1 IOH = -1 mA Output High Voltage V OH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
MIN 20 2.4
TYP 14.32
MAX 60 0.4
UNITS MHz V V
V OL IOL t r1
1
I OL = 1 mA V
OH@MIN
IOH1
1 1
= 1.0 V
-29 29 1 1 45 1.1 0.92 46.4 192
-23 27 4 4 55 1000 ns ns % ps
VOL @MIN = 1.95 V V OL = 0.4 V, VOH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V
1
t f11 dt1
1
t jcyc-cyc
V T = 1.5 V
Guaranteed by design, not 100% tested in production.
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Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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N
c
L
INDEX AREA
E1
E
12 D h x 45
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 SEE VARIATIONS D E 10.03 10.68 E1 7.40 7.60 0.635 BASIC e h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS N 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
VARIATIONS D mm. MIN MAX 18.31 18.55
D (inch) MIN .720 MAX .730
300 mil SSOP Package
Reference Doc.: JEDEC Publication 95, M O-118 10-0034
Ordering Information
ICS950703yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0690D--05/14/04
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